1. Field of the Invention
This invention relates to phase comparators and data separators for use in conjunction with phase-locked loops, and particularly to phase comparators useful at high data rates.
1. Description of the Prior Art
References:
U.S. Pat. No. 4,636,748, Jan. 13, 1987, Paul W. Latham, II, Charge Pump For Use in a Phase-Locked Loop (hereinafter "Latham", incorporated herein by reference). PA1 U.S. Pat. No. 4,568,881, Feb. 4, 1986, Anna Kostrov, Phase Comparator and Data Separator (hereinafter "Kostrov", incorporated herein by reference).
Type II phase-locked loops are commonly used for synchronizing a clock signal with a data signal. See Latham, particularly at column 1, lines 26-54, and column 2, line 55 through column 3, line 21.
An element of the phase-locked loop is the phase comparator, which generates "UP" and "DOWN" commands to the charge pump of the loop, with the UP and DOWN commands exhibiting a difference in duration proportional to the phase difference between the clock and data signals. Work has been done to speed up the operation of phase comparators rendering them suitable for use at high data rates, on the order of 100 MHz. (See Kostrov, particularly at column 1, lines 7 through 31, and column 2, line 19 through column 6, line 13.)
The fastest known prior-art phase comparator, that depicted in Kostrov's FIG. 2, requires two gate delays and one flip-flop setup time to occur within half a clock period for proper operation. For example, the DATA signal going high on lead 10 must propagate through OR-gate 32 to clock flip-flop Q1; after Q1's setup time, its Q output must propagate through OR-gate 40 to effect the UP command. Similarly, the output of OR-gate 32 primes flip-flop Q2 which triggers on the next rising edge of CLK-NOT; after Q2's setup time, its Q output must propagate through OR-gate 42 to effect the DOWN and SEPARATED DATA signals.
Kostrov states, at column 6, lines 9-13:
"Consequently, the sum of the propagation delays through flip-flop Q2, OR gate 34 and flip-flop Q1 should be no greater than about one-half of duration of the bit cell (no greater than 5 nanoseconds for a clock frequency of 100 MHz)."
To achieve this timing constraint requires a very fast state-of-the-art integrated circuit (IC) process. The present invention provides a phase comparator in which only two comparable delays are encountered, enabling it to be constructed with more common, less expensive IC process or discrete devices (or alternatively, allowing operation well in excess of 100 MHz if constructed of very fast IC process).
It is thus a general object of the present invention to provide a phase comparator useful at high speeds.
It is a particular object of the present invention to provide a phase comparator allowing half-clock periods as short as one gate delay plus one flip-flop delay time.